Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : const1
SCORELINETOGGLEBRANCH
0.00 0.00

Source File(s) :
/nfs_project/castor/DV/Farooq/Castor_V2/DV/uvm_fabric_verif_env/sim/results/../../src/IPs/eFPGA/K6N10-castor16/base/netlist/./K6N10-castor_Verilog/SRC_efpga_core/sub_module/inv_buf_passgate.v

Module self-instances :
NAMESCORELINETOGGLEBRANCH
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_8.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_8.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_9.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_9.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_0_cin_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_1_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_2_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_3_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_4_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_5_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_6_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_7_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_8_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mux_fle_9_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_0_cin_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_1_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_2_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_3_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_4_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_5_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_6_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_7_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_8_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mux_fle_9_clk_0.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_9.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_9.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mux_frac_logic_out_1.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_1_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_2_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_2_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_2_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_3_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_3_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_3_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_4_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_4_in_1.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_2__2_.logical_tile_clb_mode_clb__0.mux_fle_9_clk_0.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_2__3_.logical_tile_clb_mode_clb__0.mux_fle_2_in_2.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_2_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_5.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_3_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_4_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_5_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_6_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_7_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_8_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_5__1_.logical_tile_clb_mode_clb__0.mux_fle_9_clk_0.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_8__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_8__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_1.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_8__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_8__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_1.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_8__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_4.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_8__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_8__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_5.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_8__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_4.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_0_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_1_in_5.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_3_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_4_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_5_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_6_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_7_in_5.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_8_in_4.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_9_in_4.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_8_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_11__1_.logical_tile_clb_mode_clb__0.mux_fle_9_clk_0.const1_0_ 0.00 0.00
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tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_0_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_0_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_0_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_1_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_1_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_1_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_2_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_2_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_2_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_3_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_3_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_3_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_4_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_4_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_4_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_5_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_5_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_5_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_6_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_6_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_6_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_7_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_7_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_7_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_8_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_8_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_8_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_9_in_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_9_in_1.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_9_in_2.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_0_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_0_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_0_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_1_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_1_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_1_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_2_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_2_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_2_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_3_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_3_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_3_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_4_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_4_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_4_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_5_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_5_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_5_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_6_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_6_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_6_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_7_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_7_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_7_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_8_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_8_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_8_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_9_in_3.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_9_in_4.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_9_in_5.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_0_cin_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_1_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_2_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_3_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_4_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_5_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_6_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_7_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_8_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_clb_12__12_.logical_tile_clb_mode_clb__0.mux_fle_9_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_dsp_3__1_.logical_tile_dsp_mode_dsp__0.mux_dsp_phy_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_dsp_3__4_.logical_tile_dsp_mode_dsp__0.mux_dsp_phy_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_dsp_3__7_.logical_tile_dsp_mode_dsp__0.mux_dsp_phy_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_dsp_3__10_.logical_tile_dsp_mode_dsp__0.mux_dsp_phy_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_dsp_9__1_.logical_tile_dsp_mode_dsp__0.mux_dsp_phy_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_dsp_9__4_.logical_tile_dsp_mode_dsp__0.mux_dsp_phy_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_dsp_9__7_.logical_tile_dsp_mode_dsp__0.mux_dsp_phy_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_dsp_9__10_.logical_tile_dsp_mode_dsp__0.mux_dsp_phy_0_clk_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_bram_6__1_.logical_tile_bram_mode_bram__0.mux_bram_phy_0_CLK_A1_i_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_bram_6__1_.logical_tile_bram_mode_bram__0.mux_bram_phy_0_CLK_A2_i_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_bram_6__1_.logical_tile_bram_mode_bram__0.mux_bram_phy_0_CLK_B1_i_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_bram_6__1_.logical_tile_bram_mode_bram__0.mux_bram_phy_0_CLK_B2_i_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_bram_6__7_.logical_tile_bram_mode_bram__0.mux_bram_phy_0_CLK_A1_i_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_bram_6__7_.logical_tile_bram_mode_bram__0.mux_bram_phy_0_CLK_A2_i_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_bram_6__7_.logical_tile_bram_mode_bram__0.mux_bram_phy_0_CLK_B1_i_0.const1_0_ 0.00 0.00
tb_top.dut.i_openfpga_top.grid_bram_6__7_.logical_tile_bram_mode_bram__0.mux_bram_phy_0_CLK_B2_i_0.const1_0_ 0.00 0.00

Toggle Coverage for Module : const1
TotalCoveredPercent
Totals 1 0 0.00
Total Bits 2 0 0.00
Total Bits 0->1 1 0 0.00
Total Bits 1->0 1 0 0.00

Ports 1 0 0.00
Port Bits 2 0 0.00
Port Bits 0->1 1 0 0.00
Port Bits 1->0 1 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
const1 No No No OUTPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%